Crystal oscillators are often used to provide a clock signal in a data processing application. When such crystal oscillators are used in a real time clock application, lithium batteries are the most common source of power. Furthermore, lithium batteries have a life span of many years when the attached oscillator dissipates only a minimal amount of power. For the battery to have a maximum life expectancy, the current drawn by the oscillator must be low and typically does not exceed one micro-amp during operation. Therefore, several circuits and methodologies have been developed to reduce the power consumed by the oscillator during operation.
The power consumed by a crystal oscillator may be minimized by recognizing that the oscillator may provide the clock signal during a weak-inversion (sub-threshold) operation. During such operation, the oscillator provides a clock signal which has only a small output amplitude that is less than a transistor threshold level. The use of the clock signal with a small output amplitude provides lower power consumption, but also requires a significant amount of time to transition between logic levels. Additionally, a level shift and buffer circuit must then be added to raise the amplitude to a predetermined level and to decrease the time required to transition between logic levels. The level shift and buffer circuit can consume a significant amount of power which outweighs any power savings due to the design of this type of oscillator. Therefore, while modification of the oscillator is one method for reducing the power consumption of oscillators in data processing application, the modification does not significantly reduce the power consumption of the circuit in general due to the level shift and buffer circuit. In light of this observation, it is often necessary for the power consumption of the level shift and buffer circuit to be optimized such that the total power consumption of both the oscillator and the level shift and buffer circuit is minimized.
FIG. 1 illustrates a first prior art implementation of a first level shift and buffer circuit 10 which provides a traditional level and shift buffer circuit. First level shift and buffer circuit 10 includes two inverters 12 and 14 which are coupled via a resistor labeled "R1." Additionally, a capacitor labeled "C1" is coupled between an input signal, "Vin," and the input to inverter 14. During operation, inverter 12 establishes a DC voltage bias point. Inverter 14 amplifies the oscillator signal provided by the Vin signal. Resistor R1 and capacitor C1 form a high pass filter which allows high frequency components of the Vin signal to be amplified by inverter 12. Inverters 12 and 14 are matched so that they switch (or invert) at a same logic level.
First level shift and buffer circuit 10 consumes a significant amount of power due to a bias current drawn by inverter 12 and requires a large amount of circuit area to construct capacitor C1 and resistor R1. In an industry in which devices are required to be smaller and consume less circuit area, the presence of a large capacitor and resistor are often prohibitive in a circuit. If the sizes of the capacitor and resistor are made smaller during manufacturing, the magnitude of the Vin signal must become larger for proper operation of the circuit. Therefore, a designer must compromise either the power consumption associated with providing the Vin signal with a large magnitude or the overhead associated with consumption of surface area on a semiconductor device.
A second level shift and buffer circuit 20, commonly referred to as a Schmidtt Trigger, is illustrated in FIG. 2. FIG. 2 includes three transistors, M3, M4, and M5, as an input stage. Transistors M1 and M2 form a current mirror which allows transistor M2 to mirror the reference current, Iref, to an input stage portion of circuit 20. When in the current mirror configuration, transistor M2 effectively provides a constant current source load for the inverter formed by transistors M2, M3, M4 and M5.
When the Vin signal is logic low (zero) level, transistor M2 pulls node N1 to a logic high (one) level and the output of the Vout signal is driven to a logic low (zero) level by an inverter formed by transistors M8 and M9. As the Vin signal transitions from a logic zero to a logic one value, transistor M3 begins to conduct current and pulls node N1 toward to the reference ground voltage. As node N1 reaches a switch point of the inverter formed by transistors M8 and M9, the voltage of the Vout signal rises from a ground reference voltage. When the Vout signal exceeds a threshold voltage of transistor M4, transistor M4 begins to conduct current thereby allowing transistors M4 and M5 to assist transistor M3 in pulling node N1 to the reference ground voltage. This feedback path results in a quick transition once the Vin signal reaches a rising edge switch point. The voltage of the Vin signal when the Vout signal is rapidly switched to a logic high value is a rising edge switch point of the Schmidtt trigger.
As the voltage of the Vin signal begins to decrease, there is little effect at the Vout signal until the voltage of the Vin signal nears the falling edge switchpoint of the inverter formed by transistors M2, M3, M4, and M5. As transistors M3 and M5 begin to turn off, node N1 will begin to rise and the voltage of the Vout signal will begin to fall. When the Vout signal begins to fall, transistor M4 begins to not conduct and a conduction path between transistors M4 and M5 is effectively turned off. This feedback path allows node N1 to rise even faster and the voltage of the Vout signal transitions to a logic low value very quickly. The voltage of the Vin signal where the Vout signal rapidly switches to a logic low value is the falling edge switch point of the Schmidtt trigger. A good Schmidtt trigger will have a rising edge switch point which is significantly higher than the falling edge switch point. In a standard inverter or buffer, the rising edge and falling edge switch points are typically the same voltage.
The level shift and buffer circuit of FIG. 2 consumes a high amount of power, however, due to a high switching transient current in each of the transistors, M2, M3, M4, M5, M8, and M9. Transistors M8 and M9 especially consume a significant amount of power. When compared with the level shift and buffer circuit of FIG. 1, the level shift and buffer circuit of FIG. 2 requires less circuit area, but still consumes excess power. Therefore, a need exists for a level shift and buffer circuit which consumes lower power while requiring less circuit area.